EFFICIENT HARDWARE PRIMITIVES FOR SECURING LIGHTWEIGHT SYSTEMS

In the era of IoT and ubiquitous computing, the collection and communication of sensitive data is increasingly being handled by lightweight Integrated Circuits. Efficient hardware implementations of crytographic primitives for resource constrained applications have become critical, especially block ciphers which perform fundamental operations such as encryption, decryption, and even hashing. We study the efficiency of block ciphers under different implementation styles. For low latency applications that use unrolled block cipher implementations, we design a glitch filter to reduce energy consumption. For lightweight applications, we design a novel architecture for the widely used AES cipher. The design eliminates inefficiencies in data movement and clock activity, thereby significantly improving energy efficiency over state-of-the-art architectures. Apart from efficiency, vulnerability to implementation attacks are a concern, which we mitigate by our randomization capable lightweight AES architecture. We fabricate our designs in a commercial 16nm FinFET technology and present measured testchip data on energy consumption and side channel resistance. Finally, we address the problem of supply chain security by using image processing techniques to extract fingerprints from surface texture of plastic IC packages for IC authentication and counterfeit prevention. Collectively these works present efficient and cost effective solutions to secure lightweight systems

FPGA Side Channel Attacks without Physical Access

International audienceAs FPGA use becomes more diverse, the shareduse of these devices becomes a security concern. Multi-tenantFPGAs that contain circuits from multiple independent sourcesor users will soon be prevalent in cloud and embedded computingenvironments. The recent discovery of a new attack vector usingneighboring long wires in Xilinx SRAM FPGAs presents thepossibility of covert information leakage from an unsuspectinguser’s circuit. The work described in this paper makes twocontributions that dramatically extend this finding. First, werigorously evaluate several Intel SRAM FPGAs and confirmthat long wire information leakage is also prevalent in thesedevices. Second, we present the first successful attack on anunsuspecting circuit in an FPGA using information passively obtainedfrom neighboring long-lines. Information obtained from asingle AES S-box input wire combined with analysis of encryptedoutput is used to rapidly expose an AES key. This attack isperformed remotely without modifying the victim circuit, usingelectromagnetic probes or power measurements, or modifying theFPGA in any way. We show that our approach is effective forthree different FPGA devices. Our results demonstrate that theattack can recover encryption keys from AES circuits runningat 10MHz, and has the capability to scale to much higherfrequencies